Principal FPGA Design Engineer - Hybrid Eligible

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.

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We are seeking a talented principal engineer to join the digital design team at Draper. The successful candidate will contribute to FPGA development with an emphasis on architecture, design, simulation and test/support. Candidate must have experience using high level design and simulation tools and be familiar with process flows supporting design and similution for digital FPGA efforts. Applicant should also be familiar with embedded software development for FPGA SoCs. Preference will be given to candidates with an understanding of hardware security, signal or image processing, filter design and algorithm implementation in hardware. Direct experience with embedded FPGA design is required.

THIS IS A HYBRID ELIGIBLE POSITION.

Required Qualifications:

BSEE with 10+ years relevant experience
• Fluent in Verilog or VHDL
• Experience with design closure including timing, power and area for SWaP constrained designs
• Experience with Microchip Libero tools or ability to learn them
• Experience with Xilinx Vivado tools or ability to learn them
• Experience with SoC FPGAs
• Experience implementing digital signal processing algorithms
• Experience developing testbenches and simulating/debugging designs
• Strong analysis and problem solving skills
• Familiarity with 10Gbit Ethernet interfaces
• Experience with scripting languages
• Hybrid position with ability to be onsite as needed (mainly during hardware debug)

Preferred Qualifications:

• MSEE with 10+ years relevant experience
• Experience with Matlab/Simulink
• Experience with 10Gbit Ethernet
• UVM skills (Test and/or Test Bench Development)

Security Requirement:

Must have a current in scope DoD Secret clearance. Strong preference given to applicants with current in scope DoD Top Secret clearance.

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